[System09] system09 wishbone compatible

[John Kent]

Wishbone spec version B.3 is here:

http://www.opencores.com/downloads/wbspec_b3.pdf

Note that resets are synchronous so all the peripherals will need to be 
changed.
Synchronous resets have implications on the operation of  the ACIA I 
suspect.
I will need to assert CYC_O for 16 bit data transfers and RMW 
instructions, which means there is a bit of work required on the CPU.
Tags will be needed for interrupt acknowledge bus cycles.
I'm a little unclear on how TAGs are handled.
I currently don't distinguish interrupt acknowledge / interrupt vector 
fetch cycles.

The wishbone spec does not talk about interrupt inputs as far as I can see.

ACK_I, ERR_I and RTY_I handling will be needed on the CPU.
ACK is not a problem
RTY simply means you have to run the bus cycle again
ERR I'm not sure what to do. May be generate an NMI or just ignore it. 
I'd imagine it's used for undecoded memory.

John.

On 13/02/2010 5:39 PM, John Kent wrote:
>
> Ok ...
>
> So how should we tackle it ?
> If we go to a wishbone interface, the CPU and all the peripherals 
> should clock on the rising edge rather than the falling edge as the 
> original 68XX does.
> What are the implications of this on the Block RAM ?
>
> John.
>

-- 
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent