[System09] Simulating Xilinx designs

[John Kent]

Mike this is the procedure I used:

Start up Xilinx ISE 7.1 (or what ecver version if ISE you have)
Close any open projects
File-> Close Project

Open the Testbench project file
File -> Open Project
Navigate to C:\vhdl\System09\rtl\testbench\Testbench.ise or where ever 
you have the System09 file structure unzipped.

There will be two test benches included in the project.

Testbench1.vhd consists of a CPU and a ROM that prints out "Hello World" 
to a none existant ACIA.
Testbench2.vhd also consists of a CPU and a ROM that contains code to 
read a sector of a none existant compact flash card

The reason why you open the project file in ISE is because it will 
export the file path information to Modelsim.

Highlight testbench1.vhd in the "Sources in Project" window of ISE under 
the "Module View" tab..
In the "Processes for Source" window under the "Process View" tab, 
expand "Design Utilities" and click on the "Launch Modelsim Simulator"
Modelsim should start and you should see
a "workspace" window with "my_tsetbench" listed
an "objects" window with the signals listed and
a wave window showing the signal waveforms.

At least that is what my Modelsim does.

Highlight "my_testbench" in the "Workspace" window.
Select "Simulate->runtime options"
under the defaults tab set "Default Run" to "1 ns" and the iteration 
limit to "10000" and click "OK"
That should simulate the CPU for 10 usec.
The testbench clock has a cycle time of 200 nsec

Select "Simulate->run all"
Click on the wave window to highlight the top bar in blue
Select View->wave->zoom->zoom range
set start to "0 us" and end to "2 us" then "ok"
at the top you should see the system clock (sysclk)
You should tsee the reset initially high then go low releasing the CPU 
from reset
You should then see $FFFE on the address bus which is the reset vector 
high byte fetch of $F8 (11111000) on cpu_data_in
followed by the $FFFF reset vector low byte fetch $00 (00000000) on 
cpu_data_in
followed by the first instruction at $F800 of $8E (10001110) or LDS on 
cpu_data_in
$F801 $F8 (11111000)
$F802 $28 (00101000)
$F803 $86 LDA #$11
$F804 $11

You may have to scroll the wave display left

$F805 $B7 STA $E004
$F806 $E0
$F807 $04

You will then see the cpu_rw go low indicating a write cycle and $11 on 
cpu_data_out indicating the accumulator is being written to memory
$E004 $11

$F808 $B6 LDA $E004
$F809 $E0
$F80A $04

You will then see the read cycle at address $E004 with $11 on cpu_data_in
The reason that it reads $11 is because the ROM at $F800 repeats through 
memory
$E004 = $F804 = $11

And so it goes on.

John.

On 31/03/2010 1:28 AM, Michael Evenson wrote:
> Anyone,
>
> 	Is it possible to use ModelSim XE II 5.7c Revision 2003.03 to
> simulate the System09 design? I have tried, but I can't figure out what to
> load.
>
> Mike
>
>
>
>
> _______________________________________________
> System09 Project Home Page:
> http://members.optushome.com.au/jekent/FPGA.htm
>
> System09 mailing list
> System09 at lists.bknr.net
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>
>    

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